🧪 VHDL MCQ Quiz Hub

1. The most basic form of behavioral modeling in VHDL is _______
IF statements
Assignment statements
Loop statements
WAIT statements

2. For any concurrent assignment statement, which of the following is true?
The statement is executed once
The statement is executed twice
The value of left operand is assigned to right operand
The statement is executed as many times as the value changes

3. Which of the circuit is described by following VHDL code? LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY my_func IS PORT(x, a, b : IN std_logic; q : OUT std_logic); END my_func; ARCHITECTURE behavior OF my_func IS SIGNAL s : INTEGER; BEGIN WITH s SELECT q <= a AFTER 10 ns WHEN 0; b AFTER 10 ns WHEN 1; s <= 0 WHEN x = ‘0’ ELSE 1 WHEN x = ‘1’; END behavior;
AND gate
OR gate
MUX 2:1
DEMUX 1:2

4. The main problem with behavioral modeling is ________
Asynchronous delays
Simulation
No delay
Supports single driver only

5. What is the use of simulation deltas in VHDL code?
To create delays in simulation
To assign values to signals
To order some events
Evaluate assignment statements

6. Which function is used to create a single value for multiple driver signals?
Resolution function
Package
Concurrent assignments
Sequential assignments

7. Refer to the VHDL code given below, which of the following signal is driven by multiple drivers? LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY function IS PORT (b, c : IN BIT; a, d : OUT BIT); END function; ARCHITECTURE behavior OF my_func IS BEGIN a <= b; a <= c; d <= b; END behavior;
d
c
b
a

8. A signal is driven by two signals b and c. How the value of b and c will be resolved to calculate the value of a?
By short circuiting both driver
By open circuiting one driver
By AND operation between two drivers
By NOT operation of both drivers

9. Which of the following is default delay in VHDL?
Inertial delay
Transport delay
Delta delay
Wire delay

10. What must be overcome by the output signal to change the value in case of inertial delay?
Time
Error
Inertia
Pulse

11. The inertia value in inertial delay model is equal to _________
Initial value
Delay
Input value at a specific time
Output value at a specific time

12. Transport delay is a kind of __________
Synthesis delay
Simulation delay
Inertial delay
Wire delay

13. A buffer with single input A and single output B has a delay of 20 nanosecond. If the value of input A changes after 10 ns from 0 to 1 and it changes again from 1 to 0 at 20 ns. At what time, the value of output B will be 1, if the inertial delay model is used?
30 ns
40 ns
20 ns
Output will remain zero

14. The keyword TRANSPORT in any assignment statement specifies _______
Transport delay
Transfer the right operand immediately to left operand
Transporting the value of left operand to right operand
Inertial delay

15. A buffer with single input A and single output B has a delay of 20 nanosecond. If the value of input A changes after 10 ns from 0 to 1 and it changes again from 1 to 0 at 20 ns. At what time, the value of output B will be 1, if the transport delay model is used?
20 ns
30 ns
40 ns
Output will remain zero

16. In the VHDL code given below, which delay model is used? LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY buffer IS PORT(a : IN STD_LOGIC; b : OUT STD_LOGIC); END buffer; ARCHITECTURE buf OF buffer IS BEGIN b <= a AFTER 20 ns; END buf;
Simulation delta model
Transport delay model
Inertial delay model
Multiple driver delay model

17. For zero delay events, which of the following mechanism is used?
Transport delay mechanism
Inertial delay mechanism
Delta delay mechanism
Preemption delay mechanism

18. Which of the following delay model follows the principle of preemption?
Inertial delay
Transport delay
Delta delay
Wire delay

19. Which of the following is not the application of inertial delay?
Buffer delay
PC wire line delay
Simple delay in OR gate
Inverter delay

20. The condition to implement the simulation delta delay is _______
All events must be synchronous
The events must have at least one sequential circuit
No condition
All events must be zero delay event

21. In which part of the VHDL code, generics are declared?
Package declaration
Entity
Architecture
Configurations

22. Which of the following is correct declaration for a generic?
GENERIC (name : type := initial_value);
GENERIC (type : name := initial_value);
GENERIC (name : type <= initial_value);
GENERIC ( ype : name <= initial_value);

23. What is the main use of the generic parameter?
Defining constant type
Assigning some initial value to constant
Reusability
Using constant type within the entity

24. Which of the following is true about Generics?
Generics can be assigned information as part of simulation run
Generics cannot be assigned information as part of simulation run
Generic passes data to an entity which is not instance specific
Results of simulation can modify the value of generics

25. In most synthesis tools, only generics of type ________ are supported.
INTEGER
REAL
BIT_VECTOR
STD_LOGIC

26. GENERIC (n : INTEGER := 8); In this statement, the mode of generic ‘n’ is _______
Integer
Real
Generic
No Mode

27. Which function is used to map a generic on design?
Port map()
Generic()
Generic map()
Port

28. Generics in VHDL can be treated as _______
Global variable
Local variable
Variable
Signal

29. Which of the following can be used as a generic in a complex digital design with many inputs and two outputs?
Number of outputs
Number of inputs
Intermediate signals
No parameter

30. What do you mean by a block?
An object of architecture b)
Interconnection of two or more signals
A part of an entity
A sub module in an architecture body

31. What is the scope of variables or signals declared in the block statement?
Global to the design
Local to the architecture
Local to the block itself
Local to the entity of which architecture is defined

32. Which of the following defines the interface to the block?
Block declaration part
Block header
Block statement part
Generic declaration part

33. Guarded block has an extra ________ expression.
Conditional
Declarative
Block
Guard

34. What should be the type of the value of guard expression?
BOOLEAN
INTEGER
REAL
BIT_VECTOR

35. What is the main purpose of using blocks?
To improve reusability
To improve conditional execution
To improve readability
To improve speed of execution

36. Which of the following is better for design partitioning?
Guarded block
Unguarded block
Component instantiation
Component declaration

37. Which of the following is true about guarded blocks?
Guarded blocks can have only guarded statements
Guarded blocks can have both guarded as well as unguarded statements
Guarded blocks are executed when guarded expression is false
Guarded expression can have BIT type

38. Which of the following statement is used to describe regular structures? d)
BLOCK
GENERATE
USE
GUARDED BLOCK

39. What will be the values of out1 and out2? ARCHITECTURE bhv OF example IS CONSTANT out1 : BIT; CONSTANT out2 : BIT; BEGIN B1 : BLOCK CONSTANT S : BIT := 0; BEGIN B1-1 : BLOCK SIGNAL S : BIT := 1; BEGIN out1 <= S; END BLCOK B1-1; out2 <= S; END BLOCK B1; END bhv;
out1 = 0 and out2 = 0
out1 = 0 and out2 = 1
out1 = 1 and out2 = 0
out1 = 1 and out2 = 1

40. What is the use of FOR generation?
For describing the exceptional signals
For describing the repeating structures
For describing half adder circuit
For any exceptional cases of structure

41. Which of the following is the use of IF generation?
To handle repeating pattern of design
To handle exceptional cases of design
To design full adder circuit
To connect input instances with output

42. Which of the following is defined in structural modeling?
The structure of circuit
Behavior of circuit on different inputs
Data flow from input to output
Functional structure

43. Which of the following is not a way of partitioning a design?
Component
Block statement
Processes
Generics

44. What is the basic unit of structural modeling?
Process
Component declaration
Component instantiation
Block

45. Which of the following is similar to the entity declaration in structural modeling?
Component instantiation
Component declaration
Port map
Generic map

46. What do you mean by component instantiation?
To use the component
To describe external interface of the component
To declare the gate level components
To remove any component from the design

47. The structural model is similar to___________
Boolean relations of the circuit
Schematic block diagram of the circuit
Timing relations of the circuit
Components of the circuit

48. Which of the following is correct syntax for component declaration?
COMPONENT component_name IS PORT ( port_mode : type port_name; port_mode : type port_name; ….); END component_name;
COMPONENT component_name IS PORT ( port_mode : type port_name; port_mode : type port_name; ….); END COMPONENT;
COMPONENT component_name IS PORT ( port_name : mode type; port_name : mode type; ….); END component_name;
COMPONENT component_name IS PORT ( port_name : mode type; port_name : mode type; ….); END COMPONENT;

49. Which of the following is the correct syntax for component instantiation?
instantiate : component_name PORT MAP (port_list);
label : instantiate COMPONENT PORT MAP (port_list);
label : component_name PORT MAP (port_list);
label : instantiate component_name PORT MAP (port_list)

50. Which of the following must be known to describe a structural model in VHDL?
Number of inputs and outputs
Components and their connections
Relation between inputs and outputs
Value of output for different input combination