🧪 VHDL MCQ Quiz Hub

1. SIGNED and UNSIGNED data types are defined in which package?
std_logic_1164 package
std_logic package
std_logic_arith package
standard package

2. What is the correct method to declare a SIGNED type signal ‘x’?
SIGNAL x : IN SIGNED
SIGNAL x : IN SIGNED
SIGNAL x : IN SIGNED (7 DOWNTO 0)
SIGNAL x : IN SIGNED_VECTOR (7 DOWNTO 0)

3. What will be the value of x in the following code? SIGNAL x : IN UNSIGNED (3 DOWNTO 0 ); x <= “1101”;
12
5
-5
14

4. What will be the value of x in the following code? SIGNAL x : IN UNSIGNED (3 DOWNTO 0 ); x <= “1101”;
12
5
-5
14

5. Which of the following option is completely legal, given that a and b are two UNSIGNED type signals?
x <= a + b; y <= a – b;
x <= a OR b; y <= a AND b;
x <= a + b; y <= a OR b;
x <= a OR b; y <= a + b;

6. If a and b are two STD_LOGIC_VECTOR input signals, then legal assignment for a and b is?
x <= a.b
x <= a OR b
x <= a + b
x <= a && b

7. What do we call the data type used for representing distance, current, voltage, time, etc?
Integer
Real
Physical
Imaginary

8. What is the meaning of the base unit?
Smallest possible unit of any physical literal
SI unit of any physical literal
CGS unit for any physical literal
Fundamental building block of any design

9. Which of the following is only predefined physical literal in VHDL?
VOLTAGE
TIME
CURRENT
DISTANCE

10. SIGNAL a : REAL; which of the following is illegal assignment for a?
a <= 1.8
a <= 1.0 E10
a <= 1.0 E-10
a <=1.0 ns

11. RECORD in VHDL is similar to________ in C.
Array
File
Structure
Pointer

12. What is the difference between SIGNAL and VARIABLE?
The value of SIGNAL never varies whereas VARIABLE can change its value
SIGNAL can be used for input or output whereas VARIABLE acts as intermediate signals
SIGNAL depends upon VARIABLE for various operations
SIGNAL is global and VARIABLE is local to the process in which it is declared

13. Access types are similar to _________ in traditional programming languages.
Pointers
Arrays
Structures
Files

14. How the keyword “TYPE” is used?
TYPE datatype_name IS type_from_predefined_datatypes;
TYPE datatype_name IS datatype_range;
TYPE datatype_range IS datatype_name;
USE TYPE datatype_range IS datatype_name;

15. Which of the following is a wrong declaration for a new data type?
TYPE my_logic IS RANGE 0 to 100;
TYPE my_logic IS (‘0’, ‘1’, ‘2’);
TYPE my_logic IS ARRAY (0 TO 3) OF BIT;
TYPE my_logic IS <0 TO 20 >

16. A SUBTYPE can be defined as _________
A TYPE under a TYPE (nested)
A type of INTEGER datatype
A TYPE with some constraint
A TYPE without any constraint

17. Which of the following is the correct syntax for declaring a SUBTYPE?
TYPE type_name IS type_range AND SUBTYPE subtype_name IS subtype_range
SUBTYPE subtype_name IS subtype_range TYPE type_name
SUBTYPE subtype_name TYPE type_name IS subtype_range
SUBTYPE subtype_name IS TYPE subtype_range

18. Which of the following can’t be the value of x? Refer to the VHDL code given below. TYPE color IS (red, green, blue, black, white, gray); SUBTYPE primary IS color RANGE red to blue; VARIABLE x: primary;
White
Red
Green
Blue

19. Look at the following declarations: TYPE array1 IS ARRAY ( 0 TO 3 ) OF BIT_VECTOR (3 DOWNTO 0 ); TYPE array 2 IS ARRAY ( 0 TO 3 ) OF array1; How many total bits can be stored in these arrays?
16
9
64
27

20. Refer to the four declarations below, which of the following is not a 2 dimensional array? TYPE array1 IS ARRAY ( 3 DOWNTO 0, 1 DOWNTO 0 ) OF STD_LOGIC; TYPE array2 IS ARRAY (3 DOWNTO 0 ) OF STD_LOGIC_VECTOR( 3 DOWNTO 0 ); TYPE array3 IS ARRAY (2 DOWNTO 0 ) OF array2; TYPE array4 IS ARRAY ( 0 TO 3, 3 DOWNTO 0 ) OF BIT;
array4
array3
array2
array1

21. Which of the following is a SUBTYPE of INTEGER?
NATURAL
REAL
CHARACTER
STD_LOGIC

22. Refer to the VHDL code given below, which of the following line has error? Line 1: SUBTYPE my_logic IS STD_LOGIC RANGE ‘0’ TO ‘1’; Line 2: SIGNAL a: BIT; Line 3: SIGNAL b: STD_LOGIC; Line 4: SIGNAL c: my_logic; Line 5: b<=a; Line 6: b<=c;
Line 1
Line 4
Line 5
Line 6

23. In the VHDL code given below, what will be the error at the time of compilation? TYPE my_int IS INTEGER RANGE -32 TO 32; TYPE other_int IS INTEGER RANGE 0 TO 100; SIGNAL x : my_int; SIGNAL y : other_int; y <= x + 2;
Type mismatch
Syntax problem
No declaration
Can’t compile

24. Which of the following package of IEEE contains most of the data conversion functions?
std_logic_1164
std
std_logic_arith
std_logic

25. If we are using conv_integer(p) function, then which of the following cannot be the type of parameter ‘p’?
STD_LOGIC VECTOR
STD_ULOGIC
INTEGER
SIGNED

26. In the function conv_unsigned(p, b), what does p and b refers to?
p is the data object to be converted and b is the base of that data object
p is the data object to be converted amd b is the bits needed in converted variable
p is the parameter to be converted and b is the bits of same parameter
p is the type of data to be converted and b is the type of data into which p should be converted

27. Which of the following is the correct syntax to convert INTEGER ‘p’ into SIGNED number of ‘b’ bits?
conv_integer_signed(p,b);
conv_signed_integer(p,b);
conv_signed(p,b);
conv_signed_p(b);

28. The function conv_std_logic_vector(p,b) is used for_______
Converting ‘p’ form STD_LOGIC_VECTOR to STD_LOGIC type
Converting any data type ‘p’ into STD_LOGIC_VECTOR with ‘b’ bits
Converting STD_LOGIC_VECTOR into ‘p’ type with ‘b’ bits
Converting STD_LOGIC into STD_LOGIC_VECTOR

29. What will be the value of y after the execution of the following VHDL code? Library ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; … SIGNAL m : UNSIGNED (3 DOWNTO 0); SIGNAL n : UNSIGNED (3 DOWNTO 0); SIGNAL y : STD_LOGIC_VECTOR (7 DOWNTO 0); y <=CONV_STD_LOGIC_VECTOR ((m+n), 8);
8- bit STD_LOGIC_VECTOR m+n
8- bit UNSIGNED m+n
4- bit STD_LOGIC m+n
Error

30. Which of the following is not an assignment operator?
<=
:=
=>
=

31. A VARIABLE y is declared of STD_LOGIC_VECTOR type of 4 bits, if you want to assign 1001 to y, then what is the write assignment statement?
y <= “1001”
y := “1001”
y <= ‘1’, ‘0’, ‘0’, ‘1’
y => “1001”

32. Which of the following logical operator has the highest precedence?
NAND
NOR
NOT
EXOR

33. . In the following statements, y and z are equivalent to________ y <= NOT a AND b; z <= NOT (a AND b);
y <= a’+b’ and z <= (a.b)’
y <= (a+b)’ and z <= a’+b’
y <= a’+b and z <= a’+b’
y <= a+b’ and z <= a.b

34. Which of the following VHDL statement is equivalent to NAND operation, if y, a and b are SIGNALS?
y <= NOT a AND b
y <= NOT a OR NOT b
y <<= NOT a AND NOT b
y <<= NOT (a OR b)

35. _____ operator is unary as well as binary operator. a)
–
*
/
**

36. The operator ‘&’ is called the_____ operator.
Logical AND operator
Bitwise AND operator
Arithmetic addition operator
Concatenation operator

37. What is the type of result of MOD operator?
Numeric
Integer
Array
Bit

38. The operators like =, /=, <, >, >= are called _________
Arithmetic operators
Concatenation operators
Logical operators
Relational operators

39. What is the type of result for comparison operators?
Boolean
Integer
Numeric
Array

40. ABS operator is used to _________
Shift the operand
Gives absolute value for the operand
Give the result as nearest integer
To synthesize the result

41. Which of the following is exponentiation operator?
^
*
/=
**

42. SIGNAL x : STD_LOGIC; In this statement x is ______
Variable
Identifier
Name
Literal

43. What is the “SLL” operator?
Shift Logic Left
Shift Logically
Shift Left Logical
Shift Left

44. What is the “SLL” operator?
Shift Logic Left
Shift Logically
Shift Left Logical
Shift Left

45. The correct syntax for any logical shift operator like SLL and SRL is_____
bit_vector_operand <OPERATOR> integer_operand
integer_operand <OPERATOR> bit_vector_operand
std_logic_operand <OPERATOR> integer_operand
integer_operand <OPERATOR> std_logic_operand

46. In the following VHDL code, the values of y and z are _____ VARIABLE x : BIT_VECTOR(3 DOWNTO 0) := 1001; VARIABLE y : BIT_VECTOR(3 DOWNTO 0) := 0000; VARIABLE z : BIT_VECTOR(3 DOWNTO 0) := 0000; … y := x SRA 2; z := y SLA 2; …
y = 0000 and z = 0000
y = 1001 and z = 0000
y = 1110 and z = 0111
y = 0111 and z = 1110

47. SLL operation is equivalent to which of the following operations?
Multiplication by any natural number
Multiplication by 2
Division by 2
Exponential operation

48. Which of the following is equivalent division by 2 operator?
SRL
SLL
SLA
SRA

49. . In the VHDL code given below, what will be the values of y and z? VARIABLE x : BIT_VECTOR(3 DOWNTO 0) := 1001; VARIABLE y : BIT_VECTOR(3 DOWNTO 0) := 0000; VARIABLE z : BIT_VECTOR(3 DOWNTO 0) := 0000; … y := x ROR 2; z := y ROL 2; …
y = 0100 and z = 0000
y = 0000 and z = 0000
y = 0111 and z = 1110
y = 0110 and z = 0110

50. In a statement containing two or more operators of same precedence, how the expression will be solved?
Left to right
Right to left
Alphabetically
In a random manner

51. What will be the values of the following variables after MOD operations? x = 5 MOD 3; y = -5 MOD 3; z = 5 MOD -3;
x = 2, y = -2 and z = -2
x = 2, y = 1 and z = -2
x= 2, y = -2 and z = 2
x = 2, y = -2 and z = 1

52. What will be the values of following variables after REM operations? x = 5 REM 3; y = -5 REM 3; z = 5 REM -3;
x= 2, y = 1 and z = -2
x = 2, y = -2 and z = 1
x = 2, y = -2 and z = 2
x = 2, y = 1 and z = 1