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The most basic form of behavioral modeling in VHDL is _______

1. IF statements
2. Assignment statements
3. Loop statements
4. WAIT statements

✅ Correct Answer: 2

For any concurrent assignment statement, which of the following is true?

1. The statement is executed once
2. The statement is executed twice
3. The value of left operand is assigned to right operand
4. The statement is executed as many times as the value changes

✅ Correct Answer: 4

Which of the circuit is described by following VHDL code? LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY my_func IS PORT(x, a, b : IN std_logic; q : OUT std_logic); END my_func; ARCHITECTURE behavior OF my_func IS SIGNAL s : INTEGER; BEGIN WITH s SELECT q <= a AFTER 10 ns WHEN 0; b AFTER 10 ns WHEN 1; s <= 0 WHEN x = ‘0’ ELSE 1 WHEN x = ‘1’; END behavior;

1. AND gate
2. OR gate
3. MUX 2:1
4. DEMUX 1:2

✅ Correct Answer: 3

The main problem with behavioral modeling is ________

1. Asynchronous delays
2. Simulation
3. No delay
4. Supports single driver only

✅ Correct Answer: 1

What is the use of simulation deltas in VHDL code?

1. To create delays in simulation
2. To assign values to signals
3. To order some events
4. Evaluate assignment statements

✅ Correct Answer: 3

Which function is used to create a single value for multiple driver signals?

1. Resolution function
2. Package
3. Concurrent assignments
4. Sequential assignments

✅ Correct Answer: 1

Refer to the VHDL code given below, which of the following signal is driven by multiple drivers? LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY function IS PORT (b, c : IN BIT; a, d : OUT BIT); END function; ARCHITECTURE behavior OF my_func IS BEGIN a <= b; a <= c; d <= b; END behavior;

1. d
2. c
3. b
4. a

✅ Correct Answer: 4

A signal is driven by two signals b and c. How the value of b and c will be resolved to calculate the value of a?

1. By short circuiting both driver
2. By open circuiting one driver
3. By AND operation between two drivers
4. By NOT operation of both drivers

✅ Correct Answer: 1

Which of the following is default delay in VHDL?

1. Inertial delay
2. Transport delay
3. Delta delay
4. Wire delay

✅ Correct Answer: 1

What must be overcome by the output signal to change the value in case of inertial delay?

1. Time
2. Error
3. Inertia
4. Pulse

✅ Correct Answer: 3

The inertia value in inertial delay model is equal to _________

1. Initial value
2. Delay
3. Input value at a specific time
4. Output value at a specific time

✅ Correct Answer: 2

Transport delay is a kind of __________

1. Synthesis delay
2. Simulation delay
3. Inertial delay
4. Wire delay

✅ Correct Answer: 4

A buffer with single input A and single output B has a delay of 20 nanosecond. If the value of input A changes after 10 ns from 0 to 1 and it changes again from 1 to 0 at 20 ns. At what time, the value of output B will be 1, if the inertial delay model is used?

1. 30 ns
2. 40 ns
3. 20 ns
4. Output will remain zero

✅ Correct Answer: 4

The keyword TRANSPORT in any assignment statement specifies _______

1. Transport delay
2. Transfer the right operand immediately to left operand
3. Transporting the value of left operand to right operand
4. Inertial delay

✅ Correct Answer: 1

A buffer with single input A and single output B has a delay of 20 nanosecond. If the value of input A changes after 10 ns from 0 to 1 and it changes again from 1 to 0 at 20 ns. At what time, the value of output B will be 1, if the transport delay model is used?

1. 20 ns
2. 30 ns
3. 40 ns
4. Output will remain zero

✅ Correct Answer: 2

In the VHDL code given below, which delay model is used? LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY buffer IS PORT(a : IN STD_LOGIC; b : OUT STD_LOGIC); END buffer; ARCHITECTURE buf OF buffer IS BEGIN b <= a AFTER 20 ns; END buf;

1. Simulation delta model
2. Transport delay model
3. Inertial delay model
4. Multiple driver delay model

✅ Correct Answer: 3

For zero delay events, which of the following mechanism is used?

1. Transport delay mechanism
2. Inertial delay mechanism
3. Delta delay mechanism
4. Preemption delay mechanism

✅ Correct Answer: 3

Which of the following delay model follows the principle of preemption?

1. Inertial delay
2. Transport delay
3. Delta delay
4. Wire delay

✅ Correct Answer: 1

Which of the following is not the application of inertial delay?

1. Buffer delay
2. PC wire line delay
3. Simple delay in OR gate
4. Inverter delay

✅ Correct Answer: 2

The condition to implement the simulation delta delay is _______

1. All events must be synchronous
2. The events must have at least one sequential circuit
3. No condition
4. All events must be zero delay event

✅ Correct Answer: 4

In which part of the VHDL code, generics are declared?

1. Package declaration
2. Entity
3. Architecture
4. Configurations

✅ Correct Answer: 2

Which of the following is correct declaration for a generic?

1. GENERIC (name : type := initial_value);
2. GENERIC (type : name := initial_value);
3. GENERIC (name : type <= initial_value);
4. GENERIC ( ype : name <= initial_value);

✅ Correct Answer: 1

What is the main use of the generic parameter?

1. Defining constant type
2. Assigning some initial value to constant
3. Reusability
4. Using constant type within the entity

✅ Correct Answer: 3

Which of the following is true about Generics?

1. Generics can be assigned information as part of simulation run
2. Generics cannot be assigned information as part of simulation run
3. Generic passes data to an entity which is not instance specific
4. Results of simulation can modify the value of generics

✅ Correct Answer: 2

In most synthesis tools, only generics of type ________ are supported.

1. INTEGER
2. REAL
3. BIT_VECTOR
4. STD_LOGIC

✅ Correct Answer: 1

GENERIC (n : INTEGER := 8); In this statement, the mode of generic ‘n’ is _______

1. Integer
2. Real
3. Generic
4. No Mode

✅ Correct Answer: 4

Which function is used to map a generic on design?

1. Port map()
2. Generic()
3. Generic map()
4. Port

✅ Correct Answer: 3

Generics in VHDL can be treated as _______

1. Global variable
2. Local variable
3. Variable
4. Signal

✅ Correct Answer: 1

Which of the following can be used as a generic in a complex digital design with many inputs and two outputs?

1. Number of outputs
2. Number of inputs
3. Intermediate signals
4. No parameter

✅ Correct Answer: 2

What do you mean by a block?

1. An object of architecture b)
2. Interconnection of two or more signals
3. A part of an entity
4. A sub module in an architecture body

✅ Correct Answer: 4

What is the scope of variables or signals declared in the block statement?

1. Global to the design
2. Local to the architecture
3. Local to the block itself
4. Local to the entity of which architecture is defined

✅ Correct Answer: 3

Which of the following defines the interface to the block?

1. Block declaration part
2. Block header
3. Block statement part
4. Generic declaration part

✅ Correct Answer: 2

Guarded block has an extra ________ expression.

1. Conditional
2. Declarative
3. Block
4. Guard

✅ Correct Answer: 4

What should be the type of the value of guard expression?

1. BOOLEAN
2. INTEGER
3. REAL
4. BIT_VECTOR

✅ Correct Answer: 1

What is the main purpose of using blocks?

1. To improve reusability
2. To improve conditional execution
3. To improve readability
4. To improve speed of execution

✅ Correct Answer: 3

Which of the following is better for design partitioning?

1. Guarded block
2. Unguarded block
3. Component instantiation
4. Component declaration

✅ Correct Answer: 3

Which of the following is true about guarded blocks?

1. Guarded blocks can have only guarded statements
2. Guarded blocks can have both guarded as well as unguarded statements
3. Guarded blocks are executed when guarded expression is false
4. Guarded expression can have BIT type

✅ Correct Answer: 2

Which of the following statement is used to describe regular structures? d)

1. BLOCK
2. GENERATE
3. USE
4. GUARDED BLOCK

✅ Correct Answer: 2

What will be the values of out1 and out2? ARCHITECTURE bhv OF example IS CONSTANT out1 : BIT; CONSTANT out2 : BIT; BEGIN B1 : BLOCK CONSTANT S : BIT := 0; BEGIN B1-1 : BLOCK SIGNAL S : BIT := 1; BEGIN out1 &lt;= S; END BLCOK B1-1; out2 &lt;= S; END BLOCK B1; END bhv;

1. out1 = 0 and out2 = 0
2. out1 = 0 and out2 = 1
3. out1 = 1 and out2 = 0
4. out1 = 1 and out2 = 1

✅ Correct Answer: 3

What is the use of FOR generation?

1. For describing the exceptional signals
2. For describing the repeating structures
3. For describing half adder circuit
4. For any exceptional cases of structure

✅ Correct Answer: 2

Which of the following is the use of IF generation?

1. To handle repeating pattern of design
2. To handle exceptional cases of design
3. To design full adder circuit
4. To connect input instances with output

✅ Correct Answer: 2

Which of the following is defined in structural modeling?

1. The structure of circuit
2. Behavior of circuit on different inputs
3. Data flow from input to output
4. Functional structure

✅ Correct Answer: 1

Which of the following is not a way of partitioning a design?

1. Component
2. Block statement
3. Processes
4. Generics

✅ Correct Answer: 3

What is the basic unit of structural modeling?

1. Process
2. Component declaration
3. Component instantiation
4. Block

✅ Correct Answer: 3

Which of the following is similar to the entity declaration in structural modeling?

1. Component instantiation
2. Component declaration
3. Port map
4. Generic map

✅ Correct Answer: 2

What do you mean by component instantiation?

1. To use the component
2. To describe external interface of the component
3. To declare the gate level components
4. To remove any component from the design

✅ Correct Answer: 1

The structural model is similar to___________

1. Boolean relations of the circuit
2. Schematic block diagram of the circuit
3. Timing relations of the circuit
4. Components of the circuit

✅ Correct Answer: 2

Which of the following is correct syntax for component declaration?

1. COMPONENT component_name IS PORT ( port_mode : type port_name; port_mode : type port_name; ….); END component_name;
2. COMPONENT component_name IS PORT ( port_mode : type port_name; port_mode : type port_name; ….); END COMPONENT;
3. COMPONENT component_name IS PORT ( port_name : mode type; port_name : mode type; ….); END component_name;
4. COMPONENT component_name IS PORT ( port_name : mode type; port_name : mode type; ….); END COMPONENT;

✅ Correct Answer: 4

Which of the following is the correct syntax for component instantiation?

1. instantiate : component_name PORT MAP (port_list);
2. label : instantiate COMPONENT PORT MAP (port_list);
3. label : component_name PORT MAP (port_list);
4. label : instantiate component_name PORT MAP (port_list)

✅ Correct Answer: 3

Which of the following must be known to describe a structural model in VHDL?

1. Number of inputs and outputs
2. Components and their connections
3. Relation between inputs and outputs
4. Value of output for different input combination

✅ Correct Answer: 2

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